To achieve a larger memory capacity in a smaller chip area, some NOR type non-volatile semiconductor memory devices have a hierarchical bit line structure in which a plurality of local bit lines are connected to each of global bit lines. Described below is the working mechanism of a typical conventional n-channel floating gate type flash memory with a bit line hierarchy.
To write data, 5V, 0V, and 9V are applied to the local bit line (drain), source line, and word line (gate) for the selected cell. Electrons accelerated between the source and the drain are injected into the floating gate to cause a negative voltage, thereby decreasing the effective gate voltage applied to the gate (control gate). This increases the required gate voltage for inducing an inversion layer at the channel surface, leading to an increased threshold voltage of the memory transistor.
To erase data, the local bit line and the source line are brought into a floating state, and 9V and −9V are applied to the p-type well containing the memory transistor and the word line (gate), respectively. The negative voltage is removed as the electrons stored in the floating gate are extracted into the substrate. The threshold voltage of the memory transistor decreases, and becomes lower than that in the state when electrons were stored.
To read data, 0.9V, 0V, and 5V are applied to the local bit line (drain), source line, and word line (gate) for the selected cell. No electric current flows when the memory transistor is in written state, and a current flows when it is in erased state.
High-voltage transistors are used in the bit line control circuit since application of a voltage of 5 V to the local bit line is required to write data. Accordingly, the bit line control circuit occupies a relatively large area in the chip, restricting the reduction in chip size. To read data, on the other hand, 0.9 V is applied to the local bit line. The high-voltage transistors in the bit line control circuit are driven at a relatively low voltage, making it difficult to increase the data read speed.
High-voltage transistors are commonly used in column decoders (for instance, see Japanese Patent No. 4317745, Japanese Unexamined Patent Publication (Kokai) No. HEI-5-243531).
In a p-channel floating gate type flash memory, the drain of the memory transistor in a non-selected memory cell is in a floating state during a write process. Unexpected data writing (program disturbance) can take place if the electric potential in the drain in a non-selected memory cell comes closer to the drain voltage of the selected memory cell due to capacitive coupling with the substrate (for instance, see Japanese Unexamined Patent Publication (Kokai) No. 2008-192254).